1. Field of the Invention
The present invention relates to an image pickup apparatus.
2. Description of Related Art
A charge coupled device (CCD), a complementary metal oxide semiconductor (CMOS) sensor and the like have been used as an image pickup device, and using a plurality of pixels and making compact an image pickup device is under progress.
The increase in the number of pixels and the miniaturization of image pickup device make a unit cell size of pixels small, increase a ratio of a transistor area to a pixel area, and make the area of photodiodes small. As a result, the saturated charge amount and the sensitivity of each pixel may be lowered and an image quality may be degraded.
Japanese Unexamined Patent Application Publication No. 2006-340044 discloses a CMOS sensor (hereinafter called a CMOS sensor mounting column parallel analog to digital converters (ADCs) where applicable) having an ADC disposed every columns of pixels formed in a matrix shape, the ADCs being disposed in parallel.
FIG. 1 is a block diagram showing an example of the structure of a CMOS sensor mounting column parallel ADCs.
In FIG. 1, a CMOS sensor 11 includes a timing control circuit 12, a row scanner 13, a pixel array 14, m load MOSs 151 to 15m, a DAC (Digital Analog Converter) 16, a column processing unit 17, a column scanner 18, and a horizontal output line 19.
On the basis of a master clock having a predetermined frequency, the timing control circuit 12 supplies the row scanner 13, DAC 16, column processing unit 17, and column scanner 18, with a clock signal, a timing signal and the like necessary for the operations of these components.
The row scanner 13 sequentially supplies a signal for controlling the output of a pixel signal, to pixels disposed in a vertical direction of the pixel array 14, at a predetermined timing.
The pixel array 14 has pixels 211,1 to 21m,n having m columns and n rows: n horizontal signal lines 221 to 22n and m vertical signal lines 231 to 23m.
Each of the pixels 211,1 to 21m,n includes a photodiode (not shown). A pixel signal corresponding to an electric charge accumulated in each photodiode is outputted to each of the vertical signal lines 231 to 23m in response to a signal supplied from the row scanner 13 via each of the horizontal signal lines 221 to 22n.
The horizontal lines 221 to 22n connect the row scanner 13 to the pixels 211,1 to 21m,n in a horizontal direction. Namely, the pixels 211,1 to 21m,1 are connected to the horizontal signal line 221, the pixels 211,2 to 21m,2 are connected to the horizontal signal line 222, and in a similar manner to follow, the pixels 211,n to 21m,n are connected to the horizontal signal line 22n.
The vertical signal lines 231 to 23m connect the column processing unit 17 to the pixels 211,1 to 21m,n in a vertical direction. Namely, the pixels 211,1 to 211,n are connected to the vertical signal line 231, the pixels 212,1 to 212,n are connected to the vertical signal line 232, and in a similar manner to follow, the pixels 21m,1 to 21m,n are connected to the vertical signal line 23m.
Drains of the load MOSs 151 to 15m are connected to the vertical signal lines 231 to 23m. A bias voltage is applied to the gates, and the sources are grounded. The load MOS and an amplifying transistor (not shown) in each of the pixels 211,1 to 21m,n constitute a source follower circuit.
In accordance with a timing signal or the like from the timing control circuit 12, DAC 16 generates a ramp signal (having a waveform shown in FIG. 2 to be described later) and supplies the ramp signal to the column processing unit 17.
The column processing unit 17 includes ADCs 241 to 24m disposed in parallel, wherein the number of ADCs is m.
The ADCs 241 to 24m are connected to the vertical signal lines 231 to 23m, respectively, and perform A/D conversion of pixel signals supplied via the vertical signal lines 231 to 23m by using a ramp signal supplied from DAC 16.
The ADCs 241 to 24m each includes a comparator, a counter, a switch, and a memory. Namely, ADC 241 includes a comparator 251, a counter (CNT) 261, a switch 271, and a memory 281. The ADC 242 includes a comparator 252, a counter 262, a switch 272, and a memory 282, and in a similar manner to follow, ADC 24m includes a comparator 25m, a counter 26m, a switch 27m, and a memory 28m.
Pixel signals are supplied from the pixels 21m,1 to 21m,n to the comparators 251 to 25m, respectively, via the vertical signal lines 231 to 23m. The ramp signals from DAC 16 are supplied to the comparators 251 to 25m, respectively.
The comparators 251 to 25m compare the ramp signal supplied from DAC 16 with the pixel signals supplied via the vertical signal lines 231 to 23m, and supply comparison signals representative of the comparison results to the counters 161 to 26m. Namely, the comparator 251 supplies a comparison signal between the ramp signal from DAC 16 and the pixel signal supplied from the pixels 211,1 to 211,n via the vertical signal line 231, to the counter 261. The comparator 252 supplies a comparison signal between the ramp signal from DAC 16 and the pixel signal supplied from the pixels 212,1 to 212,n via the vertical signal line 232, to the counter 262, and in a similar manner to follow, the comparator 25m supplies a comparison signal between the ramp signal from DAC 16 and the pixel signal supplied from the pixels 21m,1 to 21m,n via the vertical signal line 23m, to the counter 26m.
The counters 261 to 26m are supplied with a clock signal from the timing control circuit 12, and count the clock signals on the basis of the comparison signal from the comparators 251 to 25m. The count values representative of the count results of clock signals by the counters 261 to 26m are supplied to the memories 281 to 28m via the switches 271 to 27m, as pixel data obtained by A/D conversion of the pixel signal.
In response to the timing signal from the timing control circuit 12, the switches 271 to 27m connect the counters 261 to 26m and the memories 281 and 28m.
The memories 281 to 28m temporarily store the pixel data supplied from the counters 261 to 26m, and output the pixel data to the horizontal output line 19 under control of the column scanner 18.
The column scanner 18 sequentially outputs the pixel data stored in the memories 281 to 28m to the horizontal output line 19 at a predetermined timing.
The horizontal output line 19 is connected to an image processing circuit or the like at the succeeding stage, and supplies the pixel data outputted from the memories 281 to 28m to an image processing circuit and the like.
FIG. 2 is a timing chart illustrating the operation of the CMOS sensor 11 shown in FIG. 1.
For example, as shown in the uppermost field of FIG. 2, during a 1 H period (one horizontal scan period), a pixel signal is read from a pixel 21N at the N-th row, and A/D converted by the column processing unit 17. During the next 1 H period, while a pixel signal is read from a pixel 21N+1 at the (N+1)-th row, pixel data obtained by A/D conversion of the pixel signal at the N-th row is outputted as shown in the second uppermost field of FIG. 2.
The pixel signal read from the pixel 21 has a waveform shown in the third field of FIG. 2, and the ramp signal outputted from DAC 16 has a waveform shown in the fourth (lowermost) field of FIG. 2. The comparator 25 in FIG. 1 compares the ramp signal with the pixel signal having these waveforms.
As described above, in the CMOS sensor 11, ADCs 241 to 24m are disposed at a pitch similar to that of the pixels 211,1 to 21m,n in the horizontal direction. As a result, the ADCs 241 to 24m perform A/D conversion of the pixel signals in parallel. As described above, as the CMOS sensor 11 mounting column parallel ADCs is made compact in recent years, the pixel array 14 is becoming small. Accordingly, a pitch of the pixels 211,1 to 21m,n in the horizontal direction becomes narrow, so that it is difficult to dispose ADCs 241 to 24m at the same pitch as that of the pixels.
Consequently, for example, the column processing unit 17 is disposed in two areas. As a result, the ADCs 241 to 24m can be disposed at a pitch wider than that of the pixels 211,1 to 21m,n in the horizontal direction.
FIG. 3 is a block diagram showing an example of the structure of a CMOS sensor 11′ having two column processing units 17A and 17B.
In FIG. 3, the CMOS sensor 11′ includes a timing control circuit 12, a row scanner 13, a pixel array 14, m load MOSs 151 to 15m, two DACs 16A and 16B, two column processing units 17A and 17B, two column scanners 18A and 18B, and two horizontal output lines 19A and 19B.
As shown in FIG. 3, in the CMOS sensor 11′ mounting column parallel ADCs, the column processing units 17A and 17B are disposed to sandwich the pixel array 14 in the vertical direction (up/down).
Although the column processing unit 17 shown in FIG. 1 includes m ADCs 241 to 24m, the column processing units 17A and 17B have each m/2 ADCs (not shown). Namely, the column processing unit 17A is provided with ADCs for A/D conversion of pixel signals at even columns among pixel signals read from the pixels 211,1 to 21m,n. The column processing unit 17B is provided with ADCs for A/D conversion of pixel signals at odd columns among pixel signals read from the pixels 211,1 to 21m,n.
In the column processing units 17A and 17B, ADCs may therefore be disposed at a pitch twice that of the pixels 211,1 to 21m,n in the horizontal direction.
The two column processing units 17A and 17B may be disposed sandwiching the pixel array 14 in the horizontal direction, or may be disposed on the same side of the pixel array 14 at two stages.
The two column processing units 17A and 17B of the CMOS sensor 11′ may have different characteristics. In this case, a photographed image may show vertical stripes, which degrades the image quality.
For example, Japanese Unexamined Patent Application Publication No. 2006-80861 discloses a CMOS sensor in which one ADC A/D converts pixels of a plurality of columns so that ADCs can be disposed at a broader pitch than that of pixels in the horizontal direction.
FIG. 4 is a block diagram showing an example of the structure of a CMOS sensor 11″ in which one ADC A/D converts pixel signals of two columns.
In FIG. 4, the CMOS sensor 11″ includes a timing control circuit 12, a row scanner 13, a pixel array 14, a column processing unit 17′, a column scanner 18, and a horizontal output line 19.
The structure of the column processing unit 17′ of the CMOS sensor 11″ shown in FIG. 4 is different from that of the column processing unit 17 of the CMOS sensor 11 shown in FIG. 1.
Namely, the column processing unit 17′ includes capacitors the number of which is m, 311 to 31m, switches the number of which is m, 321 to 32m, ADCs the number of which is m/2, 331 to 33m/2, switches the number of which is m, 341 to 34m, and memories the number of which is m, 351 to 35m.
The capacitors 311 to 31m are connected to the vertical signal lines 231 to 23m, respectively, and hold pixel signals supplied via the vertical signal lines 231 to 23m.
The switches 321 to 32m switch the connection between the capacitors 311 to 31m and ADCs 331 and 33m/2. For example, the switch 321 switches the connection between the capacitor 311 and ADC 331 and the connection between the capacitor 312 and ADC 331. When the capacitor 311 is coupled to ADC 331, the pixel signal held in the capacitor 311 is supplied to ADC 331. When the capacitor 312 is coupled to ADC 331, the pixel signal held in the capacitor 312 is supplied to ADC 331.
The ADCs 331 to 33m/2 A/D convert the pixel signals supplied from the capacitors 311 to 31m. Namely, ADC 331 A/D converts the pixel signal supplied from the capacitors 311 and 312. The ADC 332 performs A/D conversion of the pixel signal supplied from the capacitors 313 and 314, and in a similar manner to follow, ADC 33m/2 performs A/D conversion of the pixel signal supplied from the capacitors 31m-1 and 31m.
The switches 341 to 34m switch the connection between ADC 331 to 33m/2 and the memories 351 to 35m. For example, at the timing when ADC 331 A/D converts the pixel signal supplied via the vertical signal line 231, the switch 341 connects ADC 331 and memory 351. At the timing when ADC 331 performs A/D conversion of the pixel signal supplied via the vertical signal line 232, the switch 342 connects ADC 332 and memory 352.
The memories 351 to 35m temporarily store pixel data output from ADCs 331 to 33m/2, and output the pixel data to the horizontal output line 19 under control of the column scanner 18.
In the CMOS sensor 11″ constructed as above, ADCs 331 to 33m/2 can be disposed at a pitch twice that of the pixels 211,1 to 21m,n in the horizontal direction.
In the CMOS sensor 11″, the capacitors 311 to 31m hold analog pixel signals read from the pixels 211,1 to 21m,n. There may be a variation in leakage of pixel signals in the capacitors 311 to 31m, if there is a variation in capacitances of the capacitors 311 to 31m or a difference of the time from when the pixel signal is held to when the pixel signal is supplied to the ADCs 331 to 33m/2. The quality of an image photographed with the CMOS sensor 11″ may therefore be degraded.
As described above, as the unit cell size of a pixel becomes small, the area of a photodiode becomes small, and the image quality is degraded if the saturated electric charge amount and a sensitivity of a pixel are reduced.
As a method of avoiding the reduction in the saturated electric charge amount and sensitivity, there is a method of sharing a floating diffusion by using pixels in the vertical direction.
With reference to FIG. 5, description will be made on sharing a floating diffusion.
The upper area of FIG. 5 shows pixels 21N and 21N+1 having a structure that a floating diffusion is not shared. The lower area of FIG. 5 shows a pixel 21N′ having a structure that a floating diffusion is shared.
As shown in FIG. 5, the pixel 21N includes a photodiode 411, a transfer transistor 421, a reset transistor 431, an amplifying transistor 441, a select transistor 451, and a floating diffusion 461.
The electric charge corresponding to a light reception amount of the photodiode 411 is transferred to the floating diffusion 461 via the transfer transistor 421, and accumulated therein. The floating diffusion 461 is clamped to a predetermined reference potential by the reset transistor 431, and the electric charge accumulated in the reset transistor 431 is amplified by the amplifying transistor 441 and outputted to the vertical signal line 23 via the select transistor 451.
Similar to the pixel 21N, the pixel 21N+1 includes a photodiode 412, a transfer transistor 422, a reset transistor 432, an amplifying transistor 442, a select transistor 452, and a floating diffusion 462.
The pixel 21N′ includes photodiodes 411 and 412, transfer transistors 421 and 422, a reset transistor 43, an amplifying transistor 44, a select transistor 45, and a floating diffusion 46. In the pixel 21N′, the electric charge corresponding to the light reception amount of the photodiode 411 and the electric charge corresponding to the light reception amount of the photodiode 412 are alternately accumulated in the floating diffusion 46.
Thus, the pixel 21N′ shares the floating diffusion 46 so that it is possible to avoid the reduction in the saturated charge amount and sensitivity of a pixel.
However, in a CMOS sensor having a pixel array constituted of pixels sharing a floating diffusion, ADCs are disposed at the same pitch as that of pixels.